Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile (e.g., flash) memory.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates, trapping layers or other physical phenomena, determine the data state of each cell.
Due to ever increasing system speeds, memory manufacturers are under pressure to increase the bandwidth of their memory devices so that the memory does not become a speed bottleneck for the system. Memory manufacturers are also under pressure to constantly increase the memory density of the memory devices while maintaining, or even shrinking, the memory device size.
One way to increase both memory bandwidth and density is a three-dimensional structure in which the memory devices are fabricated vertically. FIG. 1 illustrates a cross-sectional view of a typical prior art semiconductor fabrication process for a memory cell string. The illustrated process can be used to vertically fabricate two strings of memory cells 120, 121.
The process forms an oxide 101 on a substrate 100. A polysilicon material 102 can be used as a select gate source (SGS) transistor for the strings of memory cells 120, 121. An etch stop material 103, formed over the polysilicon material 102, can provide an etch resistance for the polysilicon material 102 in order to slow the etching process in a future etching step.
Alternating layers 104-114 of an oxide 104, 106, 108, 110, 112 and a polysilicon 105, 107, 109, 111, 113 are formed over the etch stop 103. The polysilicon material 105, 107, 109, 111, 113 can be used as the control gates for the memory cells of the strings of memory cells 120, 121. The oxide material 104, 106, 108, 110, 112 can be used to insulate control gates of adjacent memory cells. A polysilicon material 115 is formed on top of the last oxide material 114. The top polysilicon material 115 can be used as a select gate drain transistor in the string of memory cells 120, 121.
A vertical channel 116 is formed through the top polysilicon material 115, the alternating layers of oxide and polysilicon 104-114, the etch stop layer 103, the SGS polysilicon 102, and the oxide layer 101. For purposes of clarity, only one string of memory cells 120, and only one memory cell 140 of that string 120, is subsequently described.
Recesses 130 of approximately 25 nm are formed into the control gate polysilicon 105, 107, 109, 111, 113. Each recess 130 is lined with an oxide material and filled with a polysilicon floating gate material. A polysilicon material 131 lines the vertical channel walls to connect the memory cells of the string to the lower SGS material and an oxide material is formed on the surface of the polysilicon to act as an insulator. The channel 116 is filled with a polysilicon material that is integrated with the SGS material.
Vertical fabrication of memory cell strings can enable manufacturers to form more memory cells on a memory die as compared to horizontally formed memory cell strings. While the vertically formed string of memory cells can increase memory density, using the typical prior art fabrication materials and techniques may not increase memory performance.